Network on Chips: The Journey Overview

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dc.contributor.author Mekie, Joycee
dc.contributor.author Ved, Sneha N.
dc.contributor.other 27th International Conference on VLSI Design
dc.coverage.spatial IIT Bombay, Mumbai, IN
dc.date.accessioned 2014-04-26T07:06:01Z
dc.date.available 2014-04-26T07:06:01Z
dc.date.issued 2014-01-05
dc.identifier.citation Mekie, Joycee and Ved, Sneha, “Network on Chips: The Journey Overview”, in 27th International Conference on VLSI Design, Indian Institute of Technology Bombay, Mumbai, IN, Jan. 5-9, 2014. en_US
dc.identifier.uri http://dx.doi.org/10.1109/VLSID.2014.124
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/1264
dc.description.abstract Summary form only given. This tutorial aims at highlighting the NoC journey from its origins till date. We also aim at giving an insight into the different path choices faced at different times and the preferred paths taken. With the necessary insight into the past and the present of the NoCs, we will dwell on the challenges and solutions being considered around the world. We shall also talk about the direction in which we are heading and the expected road ahead. en_US
dc.description.statementofresponsibility by Joycee Mekie and Sneha Ved
dc.language.iso en en_US
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en_US
dc.subject Asynchronous circuits en_US
dc.subject Embedded systems en_US
dc.subject Tutorials en_US
dc.subject Very large scale integration en_US
dc.title Network on Chips: The Journey Overview en_US
dc.type Article en_US


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