Design of sample and hold for 16 bit 5 Ms/S pipeline analog to digital converter

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dc.contributor.author Mohapatra, Satyajit
dc.contributor.author Gupta, Hari Shanker
dc.contributor.author Mohapatra, Nihar Ranjan
dc.contributor.author Mehta, Sanjeev
dc.contributor.author Chowdhury, Arup Roy
dc.contributor.other 2nd IEEE International Conference on "Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN-2014)
dc.coverage.spatial Surat, IN
dc.date.accessioned 2015-04-16T16:46:07Z
dc.date.available 2015-04-16T16:46:07Z
dc.date.issued 2014-12
dc.identifier.citation Mohapatra, Satyajit; Gupta, Hari Shanker; Mohapatra, Nihar R.; Mehta, Sanjeev and Chowdhury, Arup Roy, "Design of sample and hold for 16 bit 5 Ms/S pipeline analog to digital converter", in 2nd IEEE International Conference on "Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN-2014), Surat, IN, Dec. 26-27, 2014. en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/1674
dc.description.statementofresponsibility by Satyaji Mohapatra, et al
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject Digital converter en_US
dc.subject Design sample en_US
dc.title Design of sample and hold for 16 bit 5 Ms/S pipeline analog to digital converter en_US
dc.type Article en_US


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