Design of complementary high-voltage device compatible with SCL`s 0.18 um CMOS technology

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dc.contributor.advisor Mohapatra, Nihar Ranjan
dc.contributor.author Bhoir, Mandar S.
dc.date.accessioned 2016-01-01T12:57:14Z
dc.date.available 2016-01-01T12:57:14Z
dc.date.issued 2015
dc.identifier.citation Bhoir, Mandar (2015). Design of complementary high-voltage device compatible with SCL`s 0.18 um CMOS technology (M. Tech Thesis). Indian Institute of Technology, Gandhinagar, pp. 87, (T00077) en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/2048
dc.description.abstract With the advent of smart power technology and the concept of system-on-chip (SoC) for variety of applications, ranging from power management circuit and driver circuit of RF power amplifiers, integration of high voltage (HV) devices along with digital logic core has become the need of the day. Since digital logic core is implemented with continuously scaled CMOS transistors, it is a challenge to design HV devices compatible with each technology node. To server such as wise range to applications, these devices should have complementary counterparts, high breakdown voltage, low on-resistance, good DC and RF characteristics and good hot-carrier reliability. All these challenges need to be accomplished within the restriction of having none or few extra process steps, to limit the additional cost. In this work, we present optimized process-flow for complementary LDMOS transistors, which is compatible with SCL’s 0.18 um COMS process-flow. Simulation based results for N-LDMOS and P-LDMOS transistors report breakdown voltage greater than 20 v for both and ft /fMAX of 18 GHz/64 GHz and 13 GHz/49 GHZ respectively. These devices, with minimum degradation of other performance parameters, can provide breakdown voltage scalability with drift-length. Designed LDMOS transistors also provide good DC characteristics and can be easily fabricated with just two additional masks and few process steps on the top of baseline process. The designed process-flow has minimal impact of mask-misalignment, and undesirable and inseparable part of deep-submicron technologies processes. The competitive simulation results show that, these devices when fabricated would provide a cost-effective solution for applications with operating voltage upto 20 V. en_US
dc.description.statementofresponsibility by Mandar Bhoir
dc.format.extent 87 p.; col., ill; 30 cm + 1 CD ROM
dc.language.iso en en_US
dc.publisher Indian Institute of Technology Gandhinagar en_US
dc.subject Design en_US
dc.subject SCLs 0.18 um en_US
dc.subject High frequency en_US
dc.subject CMOS logic gates en_US
dc.subject CMOS technology en_US
dc.subject High-voltage device compatible en_US
dc.title Design of complementary high-voltage device compatible with SCL`s 0.18 um CMOS technology en_US
dc.type Thesis en_US
dc.contributor.department Electrical Engineering
dc.description.degree M.Tech.


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