A mismatch resilient 16-bit 20 MS/s pipelined ADC

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dc.contributor.author Mohapatra, Satyajit
dc.contributor.author Gupta, Hari Shanker
dc.contributor.author Mohapatra, Nihar Ranjan
dc.contributor.author Mehta, Sanjeev
dc.contributor.author Roy Chowdhury, Arup
dc.contributor.author Pandya, Nisha
dc.contributor.other 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID 2019)
dc.coverage.spatial Delhi, IN
dc.date.accessioned 2019-06-29T06:04:57Z
dc.date.available 2019-06-29T06:04:57Z
dc.date.issued 2019-01
dc.identifier.citation Mohapatra, Satyajit; Gupta, Hari Shanker; Mohapatra, Nihar Ranjan; Mehta, Sanjeev; Roy Chowdhury, Arup and Pandya, Nisha, "A mismatch resilient 16-bit 20 MS/s pipelined ADC", in the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID 2019), Delhi, IN, Jan. 5-9, 2019. en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/4585
dc.description.statementofresponsibility by Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury and Nisha Pandya
dc.language.iso en en_US
dc.title A mismatch resilient 16-bit 20 MS/s pipelined ADC en_US
dc.type Article en_US


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