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Analog performance of gate-first HKMG NMOS transistors - Role of device dimensions and layout

Mohapatra, Nihar Ranjan; Naresh, Satya Siva; Duhan, Pardeep (IEEE, 2015-04)

In this paper, we analyze the role of device dimensions and layout/design rules on the analog performance of HKMG NMOS transistors. We have shown ∼28% improvement in the intrinsic gain and ∼26% improvement in the gm/Id for ...
Band-to-band tunneling based ultra-energy-efficient silicon neuron

Chavan, Tanmay; Dutta, Sangya; Mohapatra, Nihar Ranjan; Ganguly, Udayan (Institute of Electrical and Electronics Engineers, 2020-06)

The human brain comprises about a hundred billion neurons connected through quadrillion synapses. Spiking neural networks (SNNs) take inspiration from the brain to model complex cognitive and learning tasks. Neuromorphic ...
Compact modeling of gate capacitance in III-V channel quadruple-gate FETs

Yadav, Chandan; Ganeriwala, Mohit D.; Mohapatra, Nihar Ranjan; Agarwal, Amit; Chauhan, Yogesh Singh (IEEE, 2017-07)

In this paper, we present a compact model for charge density and gate capacitance for low effective mass channel material based quadruple-gate FETs (QGFETs). The proposed model accounts for the effect of quantum capacitance ...
A computationally efficient compact model for trap-assisted carrier transport through multi-stack gate dielectrics of HKMG nMOS transistors

Ojha, Apoorva; Mohapatra, Nihar Ranjan (IEEE, 2018-09)

This paper analyzes in detail the carrier transport through the multi stack gate dielectric of High-K Metal gate (HKMG) nMOS transistors under different gate biases and temperatures. The existing uncertainty about the ...
PBTI in HKMG nMOS transistors--effect of width, layout, and other technological parameters

Duhan, Pardeep; Rao, V. Ramgopal; Mohapatra, Nihar Ranjan (IEEE, 2017-10)

This paper discusses in detail the effects of transistor width, layout, and technological parameters like gate dielectric and Lanthanum capping layer thickness on positive bias temperature instability (PBTI) of nMOS ...
Source underlap-a novel technique to improve safe operating area and output-conductance in LDMOS transistors

Bhoir, Mandar S.; Kaushal, Kumari Neeraj; Panda, Soumya R.; Singh, Amit K.; Jatana, H. S.; Mohapatra, Nihar R. (Institute of Electrical and Electronics Engineers, 2019-11)

In this article, we have proposed a simple, novel, and cost-effective technique to mitigate the ON-state performance issues in laterally diffused MOS (LDMOS) transistors. We propose a novel technique-LDMOS transistor with ...
Width and layout dependence of HC and PBTI induced degradation in HKMG nMOS transistors

Duhan, Pardeep; Ramgopal Rao, V.; Mohapatra, Nihar Ranjan (IEEE, 2016-04-17)

This paper discusses in detail the effects of transistor width and layout on the Hot-Carrier (HC) and Positive Bias Temperature Instability (PBTI) induced degradation in nMOS transistors fabricated using a 28-nm gate-first ...

Now showing items 1-7 of 7

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