Upset hardened dual-interlocked cell (DICE) [1] has found an important place in circuits for space applications due to its ability to mitigate single event upsets (SEUs). In this paper, we show that DICE latch/flip-flop ...

This paper discusses in detail the effects of transistor width and layout on the Hot-Carrier (HC) and Positive Bias Temperature Instability (PBTI) induced degradation in nMOS transistors fabricated using a 28-nm gate-first ...