Effect of Sub-10nm Fin-widths on the Analog Performance of FinFETs

This work experimentally investigates the effect of fin-width (W<inf>fin</inf>) scaling in sub-10nm regime on the analog performance of nFinFETs. It is shown that the device trans-conductance (g<inf>m</inf>) degrades and output conductance (g<inf>ds</inf>) improves with reduction in W<inf>fin</inf>. Various sources affecting the variability of g<inf>m</inf> and g<inf>ds</inf> in sub-10nm W<inf>fin</inf> regime are also explored. Through different analog performance metrics, it is shown that the analog performance of thinner fin FinFETs can be further increased by properly optimizing the S/D resistance and gate dielectric.