Mohapatra, SatyajitSatyajitMohapatraGupta, Hari ShankerHari ShankerGuptaMohapatra, Nihar RanjanNihar RanjanMohapatra2025-08-302025-08-302018-08-07[9781538670996]10.1109/ISVLSI.2018.000412-s2.0-85052069379http://repository.iitgn.ac.in/handle/IITG2025/22793Modern data converters architectures like pipeline ADC and Current steering DAC depend on component matching to achieve desired resolution. They consist of large arrays of capacitors/current sources that are highly susceptible to systematic effects arising from process variations and temperature gradients. On top of it, 3D integration of mixed signal ICs adjacent to digital chips makes the arrays are prone to local gradients and hot spots. This makes incorporation of certain error compensation schemes at a layout level a priority. In this work, we have proposed an arraying technique that simultaneously compensates for systematic effects and perform significantly better in the presence of rotated parabolic gradients and localized hotspots. We further propose a modified switching scheme that enables realization of 3.5-bit CFCS decoder circuit with minimum logic gates and delay. The performance of the proposed array integrated with the modified switching scheme is verified on the model of a 16-bit 10Msps pipelined ADC using Matlab. The simulation results show significant improvement of linearity (~6-12 dB) over the existing techniques. The various design challenges and strategies to overcome them are discussed in detail.falseCapacitor Mismatch | CMOS process | Commutated Feedback Capacitor Switching (CFCS) | Hotspot | Merged Capacitor Switching(MCS) | Oxide Gradient | Pipelined ADCConference Paper21593477175-1807 August 201858429362cpConference Proceeding5