Singh, HarshvardhanHarshvardhanSinghSolanki, NirmalNirmalSolankiMaskeen, Jaskirat SinghJaskirat SinghMaskeenSaini, ShaluShaluSainiPathak, MadhavMadhavPathakLashkare, SandipSandipLashkare2025-12-102025-12-102026-03-0110.1016/j.mee.2025.1124292-s2.0-105023587986http://repository.iitgn.ac.in/handle/IITG2025/33603Spiking Neural Networks (SNNs) inspired by the human brain are promising alternative to solve real-life complex problems, such as pattern recognition at low energy consumption. A key approach to implementing SNNs involves using a Resistance Random Access Memory (RRAM) crossbar array to simulate synaptic weights, which can have multi-step resistance states suitable for processing analog signals. However, a major hurdle with traditional 2-terminal RRAMs is the “read–write dilemma”: the low voltage needed for a non-destructive read operation conflicts with the high voltage required for a write operation, making simultaneous, real-time learning challenging. Current solutions to this problem, such as time or frequency division multiplexing and separate read/write arrays, increase the circuit’s complexity, size, or operation time. This paper proposes a novel solution using a recently developed 3-terminal (3T) Pr<inf>0.7</inf>Ca<inf>0.3</inf>MnO<inf>3</inf> (PCMO) RRAM. By using two terminals for writing and a third, dedicated decoupled terminal for reading, this architecture allows for simultaneous and asynchronous read and write operations. This approach resolves the read–write conflict inherent in 2-terminal designs, enabling real-time learning in SNNs without significant increase in circuit overhead and learning time.falseCrossbar array | Neuromorphic engineering | RRAM | Spike-timing dependent plasticity | Spiking Neural NetworkArticle1 March 20260112429WOS:001633438000002