Mohapatra, Nihar R.Nihar R.MohapatraNaresh, Satya SivaSatya SivaNareshDuhan, PardeepPardeepDuhan2025-08-302025-08-302015-06-03[9781479973750]10.1109/VLSI-TSA.2015.71175762-s2.0-84940775291http://repository.iitgn.ac.in/handle/IITG2025/21450In this paper, we analyze the role of device dimensions and layout/design rules on the analog performance of HKMG NMOS transistors. We have shown ∼28% improvement in the intrinsic gain and ∼26% improvement in the g<inf>m</inf>/I<inf>d</inf> for an 80nm wide transistor compared to a 1μm wide one. We have also shown that the analog performance of transistors could be improved further by dividing a single active into multiple active fingers, by increasing the active to active spacing and by eliminating the active dummies.falseConference Paper3 June 201507117576cpConference Proceeding0