Duhan, PardeepPardeepDuhanRao, V. RamgopalV. RamgopalRaoMohapatra, Nihar R.Nihar R.Mohapatra2025-08-302025-08-302016-09-22[9781467391368]10.1109/IRPS.2016.75746492-s2.0-84990902984http://repository.iitgn.ac.in/handle/IITG2025/21827This paper discusses in detail the effects of transistor width and layout on the Hot-Carrier (HC) and Positive Bias Temperature Instability (PBTI) induced degradation in nMOS transistors fabricated using a 28-nm gate-first HKMG CMOS technology. It is observed that the HC and PBTI induced degradation reduces with reduction in the width of HKMG nMOS transistors. The physical mechanisms behind this width dependence are attributed to reduction in the number of defect states in HfO2 for narrow width transistors. It is also shown that the long term reliability of the HKMG nMOS transistors could be further improved by dividing a single active into multiple actives, by increasing the active-to-active spacing and gate pitch.falsechannel width | charge trapping | high-k dielectric | hot carrier injection | metal gates | oxygen vacancies | PBTI | threshold voltageConference PaperXT071-XT07522 September 2016575746494