Maheshwari, OmOmMaheshwariDr Nihar Ranjan Mohapatra2025-12-032025-12-032025-01-01[9798331548834]10.1109/SISPAD66650.2025.111860162-s2.0-105022441861http://repository.iitgn.ac.in/handle/IITG2025/33579This work presents a robust machine learning (ML) framework for modeling the inner spacer etch process and its impact on electrical behavior in gate-all-around (GAA) FETs. Leveraging an in-house Process Monte Carlo (PMC) simulator, the etch front evolution under diverse process conditions is simulated. Gaussian Process Regression (GPR) demonstrates superior accuracy (98.5%) in modeling inner spacer etch process. Artificial Neural Networks (ANNs) are employed to map inner spacer etch geometric variations to device current characteristics with 98.2% accuracy. The proposed ML pipeline establishes a direct process-to-device link, enabling accurate assessment of electrical performance variations, and paving the way for data-driven process-performance co-optimization in advanced transistor technologies.falseANN | gate all around FETs | GPR | inner spacer etch | NSFET | particle monte-carlo | process variationConference Paper1946157720250