Glint, TomTomGlintSah, JiteshJiteshSahAwasthi, ManuManuAwasthiMekie, JoyceeJoyceeMekie2025-08-312025-08-312020-10-01[9781728197104]10.1109/ICCD50377.2020.001072-s2.0-85098870285http://repository.iitgn.ac.in/handle/IITG2025/25683In a large chip, an asynchronous Network-on-Chip (NoC) is a suitable candidate for establishing an interconnection network between varied components. Architectural level simulation is an accepted methodology for evaluating such systems. In this paper, we propose a fast and versatile Asynchronous Network-on-Chip (NoC) Simulator - ANSim, which brings down the simulation time by 25 x, compared to the state of the art simulators. It can model and analyze all synchronous, asynchronous, and mixed synchronous-asynchronous system of cores connected through NoC. ANSim can model routers with different delays, routers with asynchronous arbitration, connected in a wide range of topologies. ANSim supports individual routers modeled to have varying timing constraints. Further, it supports synthetic and real-workloads, and produces system-level latency, throughput, power, power-gating, and arbitration reports. ANSim has been verified against RTL models of NoCs, and other RTL verified simulators. An open-source synchronous NoC router, TNoC, and its asynchronous derivative are used to demonstrate ANSim's usefulness and features.falseAsynchronous NoC | metastability | SimulatorConference Paper619-622October 202039283570cpConference Proceeding2