Jha, Chandan KumarChandan KumarJhaPrasad, KailashKailashPrasadSrivastava, Vibhor KumarVibhor KumarSrivastavaMekie, JoyceeJoyceeMekie2025-08-312025-08-312020-01-01[9781728133201]2-s2.0-85108993322http://repository.iitgn.ac.in/handle/IITG2025/25706Approximate computing has emerged as a unique proposition for error-resilient applications such as image/video processing, neural networks, and the like, where both performance and power can be simultaneously reduced by trading off output quality. In this paper we propose a multistage approximation methodology for designing IEEE 754 floating point approximate dividers (FPADs). We propose a number of FPADs with varying upper bounds on error. For the same mean error, FPAD is 2.84× better in terms of power-delay product (PDP) as compared to state of the art approximate floating point divider. Further, when applied on applications, such as image enhancement, mean filtering and JPEG compression, FPAD outperforms the existing state-of-the-art approximate divider in terms of PDP by 25%. We also show that FPAD gives same PDP benefits in Alexnet convolutional neural network without noticeable drop in top-5 and top-1 accuracy.falseConference Paper2020129180768cpConference Proceeding