Bhoir, Mandar S.Mandar S.BhoirMohapatra, Nihar R.Nihar R.MohapatraChiarella, ThomasThomasChiarellaRagnarsson, Lars �keLars �keRagnarssonMitard, JeromeJeromeMitardTerzeiva, ValentinaValentinaTerzeivaHoriguchi, NaotoNaotoHoriguchi2025-08-312025-08-312019-03-01[9781538665084]10.1109/EDTM.2019.87312002-s2.0-85067816806http://repository.iitgn.ac.in/handle/IITG2025/23340This work experimentally investigates the effect of fin-width (W<inf>fin</inf>) scaling in sub-10nm regime on the analog performance of nFinFETs. It is shown that the device trans-conductance (g<inf>m</inf>) degrades and output conductance (g<inf>ds</inf>) improves with reduction in W<inf>fin</inf>. Various sources affecting the variability of g<inf>m</inf> and g<inf>ds</inf> in sub-10nm W<inf>fin</inf> regime are also explored. Through different analog performance metrics, it is shown that the analog performance of thinner fin FinFETs can be further increased by properly optimizing the S/D resistance and gate dielectric.falseConference Paper7-9March 201918731200cpConference Proceeding1