Analog CMOS multiplier circuits: design and comparative analysis

Nithin P.Pathak, MadhavMadhavPathak2026-03-132026-03-132025-12-1310.1109/ICEE67165.2025.11409824https://repository.iitgn.ac.in/handle/IITG2025/34823en-USAnalog MultiplicationsTrans-linear PrincipleNeural NetworkSubthreshold OperationProcess VariationMismatchIntegrated CircuitsAnalog CMOS multiplier circuits: design and comparative analysisConference Paper