Senapati, AsimAsimSenapatiDas, ApuApuDasKumar, GauthamGauthamKumarLou, Zhao-FengZhao-FengLouMuller, JonasJonasMullerMaskeen, Jaskirat SinghJaskirat SinghMaskeenChang, Yii-TayYii-TayChangTewari, MohitMohitTewariAgarwal, AnkitAnkitAgarwalRaffel, YannickYannickRaffelMaikap, SidhdheswarSidhdheswarMaikapKao, Kuo-HsingKuo-HsingKaoAgarwal, TarunTarunAgarwalLashkare, SandipSandipLashkareLu, DarsenDarsenLuLarrieu, GuilhemGuilhemLarrieuLee, Min-HungMin-HungLeeDe, SouravSouravDe2025-11-272025-11-272025-1110.36227/techrxiv.176315919.92028806/v1http://repository.iitgn.ac.in/handle/IITG2025/33564Ferroelectric hafnia transistors are widely regarded as candidates for nonvolatile memory and in-memory compute, yet their behavior under deep-cryogenic operation at advanced gate scaling remains insufficiently resolved. Here we report ferroelectric fieldeffect transistors (FeFETs) with sub-2 nm equivalent-oxide thickness (EOT) gate stacks incorporating ?5 nm Hf-Zr oxide that switch robustly at 10 K, delivering memory windows exceeding 1 V, tightly distributed thresholds (standard deviation < 40 mV), endurance beyond 10 7 cycles, and cryogenic retention consistent with decade-scale projections. Correlative 4D-STEM phase mapping and X-ray photoelectron spectroscopy trace the performance to a low-temperature increase of the orthorhombic ferroelectric fraction after electrical wake-up, indicative of stabilized polarization and strengthened oxygen-metal coordination. Time-voltage sweeps delineate a practical design window: the memory window saturates beyond ? �5 V programming and ? 900 ns pulse width, consistent with nucleation-limited reversal kinetics in ultrathin films. Reliability maps identify a read-bias (V DS)-driven endurance limit arising from lateral-field-assisted trapping near the drain, which is mitigated by low-V DS read conditions. Finally, a spiking-neural-network demonstration at 10 K achieving >92% classification accuracy underscores system-level utility. Together, these results establish sub-2 nm-EOT hafnia FeFETs as a viable platform for energy-efficient cryogenic memory and neuromorphic computing, and provide concrete device-level guidelines for integration within quantum-classical heterogeneous systems.en-USe-Print