Accelerated Bit Slicing Technique for In-Memory Computing Using Multi-Input Resistive Random Access Memory

Sakhuja, JayatikaJayatikaSakhujaJoglekar, RadhikaRadhikaJoglekarLashkare, SandipSandipLashkareGanguly, UdayanUdayanGanguly2025-08-312025-08-312024-01-01[9798350371529]10.1109/EDTM58488.2024.105114442-s2.0-85193243694http://repository.iitgn.ac.in/handle/IITG2025/29201Recently, there has been a strong focus on enhancing computing efficiency with emerging memristor devices. In this paper, we propose accelerated bit-slicing technique using multi-input memristor in crossbar arrays. First, we demonstrate bit slicing in standard 2-terminal(T) PCMORRAM, wherein each bit (of n-bit input) is serially computed. Second, we introduce 3T-RRAM (two-inputs), allowing simultaneous computation of 2-bits resulting in reduction of processing cycles. Lastly, accelerated computation of 6-bit input in 3-cycles is demonstrated with 3T-RRAM.false3T-RRAM | bit slicing | IMC | PCMO | VMMAccelerated Bit Slicing Technique for In-Memory Computing Using Multi-Input Resistive Random Access MemoryConference Paper20240cpConference Proceeding0