Kaushal, Kumari NeerajKumari NeerajKaushalMohapatra, Nihar R.Nihar R.Mohapatra2025-08-312025-08-312022-01-0110.1109/TED.2021.31313022-s2.0-85121340962http://repository.iitgn.ac.in/handle/IITG2025/25150This article reviews and provides physical insights into the anomalous capacitance behavior of laterally diffused MOS (LDMOS) transistors. It is shown that the modulation of channel/drift junction potential with ${V}_{G}$ , ${V}_{D}$ , and ${V}_{S}$ is primarily responsible for the capacitance peaks observed at different bias conditions. The ${V}_{\text {GS}}$ at which these capacitances peak and their magnitude depends on the channel doping gradient (CDG) and drift region parameters. Simple mathematical models valid across all bias regimes are proposed to explain the anomalous behavior. Different LDMOS device designs are also suggested to mitigate or delay the capacitance peaks.falseCapacitance peak | channel doping gradient (CDG) | drift resistance | field plate | laterally diffused MOS (LDMOS) | space charge modulation (SCM) | unified capacitance theoryArticle1557964639-441 January 202213arJournal13WOS:000732626400001