Mohapatra, Nihar RanjanSoni, AshishAshishSoni2025-09-042025-09-042017-01-01http://repository.iitgn.ac.in/handle/IITG2025/32134An increasing trend of sensing biomedical signals with portable handheld devices has created strong demand for highly energy efficient data converters. This work presents the design and simulation of an ultra-low powered 14 bit 5KS/s fully differential asymmetric multi-split SAR ADC in SCL 180nm single poly four metal CMOS processes. It drives ADC design methodology towards the advance calibration approach and compromises with SNDR. This paper deals with critical design techniques for achieving high FOM at very low power consumption without compromising with linearity. Integrated transient response of Charge Redistribution Split-DAC shows settling accuracy of 122 V within 5.88 s while consuming only 2.66 W. The design is implemented using cadence virtuoso and functionality testing is done in Cadence Analog Design Environment. The robustness of design has been verified by PVT and Monte Carlo analysis with no missing codes. Split SAR optimization techniques, high-speed comparator design, and asymmetric multi-split capacitive DAC is used to achieve ultra low power. Design methodology for achieving ultra-low power consumption and good linearity are discussed in details.29 cm.15210023Semiconductor TechnologySCL 180nm CMOSCadence VirtuosoAsymmetric Capacitive DACPortable Handheld DevicesM.Tech75p.M.Tech123456789/500