Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA

Glint, TomTomGlintGupta, AryanAryanGuptaGiftson, DanielDanielGiftsonShah, GauravGauravShahPatel, VrajeshVrajeshPatelChudasama, RuchitRuchitChudasamaMore, SukanyaSukanyaMoreMekie, JoyceeJoyceeMekie2025-08-312025-08-312023-01-01[9798350397390]10.1109/ISPASS57527.2023.000422-s2.0-85164538124http://repository.iitgn.ac.in/handle/IITG2025/26946Due to their flexibility, FPGAs are used to deploy Deep Neural Network Accelerators (DA) at various compute locations such as servers and edge computes. In this work, we show the impact of choosing architectural parameters on performance metrics for SOTA DA implemented on FPGA, and the optimal design point for maximum compute throughput.falseDNN Accelerator | FPGAImpact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGAConference Paper328-33020230cpConference Proceeding0