Soni, AshishAshishSoniUmap, AbhijitAbhijitUmapMohapatra, Nihar R.Nihar R.Mohapatra2025-08-302025-08-302017-01-01[9789811074691]10.1007/978-981-10-7470-7_232-s2.0-85039424831http://repository.iitgn.ac.in/handle/IITG2025/23030Sequential circuits like pulsed latches and semi-dynamic flip-flops are extensively used in state-of-the-art high performance microprocessors. In this paper, we proposed a novel approach of exploiting the metal gate workfunction to reduce the power consumption and area of the pulsed latches and semi-dynamic flip-flops made using FinFETs. Compared to the design using standard shorted gate FinFETs, the proposed pulsed latch reduces the dynamic and leakage power by 37% and 42% respectively. Similarly, the proposed semi-dynamic flip-flop shows a reduction of 24% and 32% respectively in dynamic and leakage power consumption compared to the standard design. The proposed circuits also show significant improvement in static noise margin and reduction in area.falseFinFETs | Pulsed latch (PL) | Semidynamic flip-flop (SDFF) | Shorted gate FinFET (SG-FinFET) | Workfunction engineering (WFE)Conference Paper227-23820170cpBook Series0