System-level analysis of dual node upset tolerant flip-flops

Mekie, JoyceeAgarwal, AyushAyushAgarwal2025-09-042025-09-042021-01-01http://repository.iitgn.ac.in/handle/IITG2025/32244ill.; hbk.; 30 cm.19210072Circuits and SystemsCMOS technologyMicroelectronicsNuclear ScienceAdaptive HardwareSystem-level analysis of dual node upset tolerant flip-flopsM.Techxiii, 81p.M.Tech123456789/500