Effect of Device Geometries on HCI and PBTI of Gate First High-K Metal Gate NMOS Transistors

Show simple item record

dc.contributor.advisor Mohapatra, Nihar Ranjan
dc.contributor.author Jain, Sharad Kumar
dc.date.accessioned 2014-09-16T10:32:39Z
dc.date.available 2014-09-16T10:32:39Z
dc.date.issued 2014-06
dc.identifier.citation Jain, Sharad Kumar (2014). Effect of Device Geometries on HCI and PBTI of Gate First High-K Metal Gate NMOS Transistors(M. Tech. Dissertations). Indian Institute of Technology, Gandhinagar, pp. 59 (Acc No: T00023) en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/1400
dc.description.abstract As the scaling of MOS transistor is approaching the physical limits, large leakage current is becoming a major obstacle. Therefore, high-K materials have been introduced as gate dielectrics in the transistors to further continue technology miniaturization. However, reliability of MOS transistors with high- K/Metal gate structure has become a serious concern, because of more defects in gate dielectric, and introduction of capping layers (La for NMOS and Al for PMOS). Hot carrier injection (HCI) and bias temperature instability (BTI) still remain the key reliability issues. In recent technology nodes, the Positive BTI (PBTI) component cannot be avoided in HCI stress, and this seriously affects the accurate life time prediction of the device. This work aims at decoupling of the PBTI component from HCI stress using their distinct behaviour at elevated temperature. A unique trend of HCI degradation with the variation in the device width has been shown where wider devices are more prone to degradation. It can be due to more number of nonuniformly distributed oxygen vacancies present in the wider devices. It has also been observed that increase in capping layer (La) thickness in the NMOS transistor increases the total degradation and we have attributed this to the stress induced trap generation in the bulk oxide. en_US
dc.description.statementofresponsibility by Sharad Kumar Jain
dc.language.iso en en_US
dc.publisher Indian Institute of Technology, Gandhinagar en_US
dc.subject Gate en_US
dc.subject HCI en_US
dc.subject High-K Metal en_US
dc.subject PBTI of Gate en_US
dc.title Effect of Device Geometries on HCI and PBTI of Gate First High-K Metal Gate NMOS Transistors en_US
dc.type Thesis en_US
dc.contributor.department Electrical Engineering
dc.description.degree M.Tech.

Files in this item

Files Size Format View

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record

Search Digital Repository


My Account