Analysis and Modeling of Stress Overlayer Induced Threshold Voltage Shift in High-K Metal Gate MOSFETs

Abstract

Uniaxial process induced stress along with high-K Metal Gate has been extensively adopted for 45nm and below CMOS technology node to improve the performance of deep sub-micron devices. Stress generates strain in the MOSFET channel which alters the bandstructure of silicon and improves the performance by enhancing the carrier mobility. Incorporation of process induced stress using stressed overlayer has become very popular due to its ease of implementation in standard CMOS process flow. Traditionally, process induced stress was preferred because of its less bandgap narrowing and hence less threshold voltage shift compare to substrate induced biaxial stress. However, in case of devices with high-K metal gate along with stressed overlayer the experimental data shows a large threshold voltage shift. Various models have already been proposed to calculate the threshold voltage shift by in-plane uniaxial stress. Note that the large threshold voltage shift owing to stressed overlayer and high-K metal gate devices cannot be explained by conventional in-plane uniaxial stress model. This is because the stressed overlayer also generates a significant out-of-plane transverse stress along with the in-plane uniaxial stress. In this work, the stress transfer mechanism of stressed overlayer and the physics behind the large threshold voltage shift are explained. A model has been proposed to calculate the threshold voltage shift due to stressed overlayer for [110] channel oriented devices for a (100) wafer. The proposed model considers the effects of conventional in-plane uniaxial stress along with out-ofplane transverse stress generated by stressed overlayer.