Design and Implementation of Efficient Neuromorphic Architectures

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dc.contributor.advisor Mekie, Joycee
dc.contributor.author Tunga, Chandra Sekhar
dc.date.accessioned 2015-08-31T16:19:32Z
dc.date.available 2015-08-31T16:19:32Z
dc.date.issued 2015
dc.identifier.citation Tunga, Chandra Sekhar, (2015). Design and Implementation of Efficient Neuromorphic Architectures, (M. Tech. Dissertation).'Indian Institute of Technology, Ganadhinagar, pp. 59 (Acc No: T00069) en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/1877
dc.description.abstract Neuromorphic architectures have recently gained attention due to cognitive computing which requires parallel and distributed architectures. Eventbased neuromorphic architectures generally use Address-Event-Representation (AER) and encode the neuron events to efficiently communicate them on a single channel. The existing work on neuromorphic designs have focused on biologically-plausible neuron design or on address-event communication. Generally these designs have been tested on ASICs. However, the turn-around time and cost of ASIC designs are exhorbitant. On the other hand, the scalability of the neuromorphic architecture is limited due to interconnect (wire) delays when implemented as an ASIC. In this work, we present a novel implementation of asynchronous neuromorphic architecture on a synchronous FPGA. We propose a highly efficient automated approach to reduce the space utilization on the FPGA. Generally neurons in a neuromorphic architecture are arranged in rows and columns, and hence we refer to them as 2D neuromorphic architectures. In this work, we discuss the latency, scalability and power issues of conventional 2D neuromorphic architectures. We present a new three-dimensional (3D) neuromorphic architecture with a virtual third dimension called layer, which is highly scalable and allows significant reduction in latency to the conventional approach. A complex neuromorphic architecture with 625 neurons (25 25 neurons), along with address-event communication protocol has been implemented on the state-of-the-art 28 nm Kintex KC-705 board. We demonstrate that the proposed 3D architecture is highly tunable for power, performance and accuracy, and can be scaled up to 100 100 neurons. en_US
dc.description.statementofresponsibility by Chandra Sekhar Tunga
dc.format.extent by Chandra Sekhar Tunga
dc.language.iso en_US en_US
dc.publisher Indian Institute of Technology, Ganadhinagar en_US
dc.subject Neuromorphic en_US
dc.subject Architecture en_US
dc.subject Address-Event-Representation, en_US
dc.subject Asynchronous en_US
dc.subject Synchronous en_US
dc.subject FPGA en_US
dc.title Design and Implementation of Efficient Neuromorphic Architectures en_US
dc.type Thesis en_US
dc.contributor.department Electrical Engineering
dc.description.degree M.Tech.


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