Anomalous narrow width effect in gate first high-K metal gate MOS transistors

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dc.contributor.advisor Mohapatra, Nihar Ranjan
dc.contributor.author Satya Sivanaresh, M.
dc.date.accessioned 2017-03-22T10:23:19Z
dc.date.available 2017-03-22T10:23:19Z
dc.date.issued 2016
dc.identifier.citation Satya Sivanaresh M. (2016). Anomalous narrow width effect in gate first high-K metal gate MOS transistors (PhD Thesis). Indian Institute of Technology, Gandhinagar, pp. 143 (Acc No: T000179) en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/2723
dc.description.abstract HIGH K dielectrics and metal gate stacks (HKMG stacks) are currently being used in place of conventional silicon dioxide and poly-silicon gate stacks (SiO2/Poly gate stack) for 45nm or below CMOS technology generations. The transistor dimensions (length and width) are small and also continuously shrinking in these technology generations. Therefore, the deeply scaled geometries coupled with HKMG stack give rise to many anomalous effects. These anomalous effects were never observed in earlier nodes. One of these effects is increase in both the threshold voltage (VT) and the trans-conductance (gm) with decrease in the transistor width (W) of nMOS transistors. The main focus of this thesis is to study and understand the details of the Narrow Width Effect (NWE) observed in HKMG MOS transistors and to access its impact on the analog/ digital circuit performance. We have studied and explained in detail different geometry effects exhibited by the HKMG MOS transistors fabricated using a 28nm gate first CMOS technology. It is shown that the VT of the nMOS transistors increases with the decrease in channel width (W) and this effect is amplified with the reduction in gate lengh (LG). The pMOS transistors show decrease in│VT│with the reduction in width. It is also shown that this NWE is enhanced for nMOS and pMOS transistors with thicker HfO2 film and thicker capping layer. Through detailed measurements on different test structures, the reason behind this anomalous behavior is attributed to the annihilation of positively charged oxygen vacancies (V0++) and interface dipoles in the gate dielectric stack at the corners of the gate-active overlap region after post gate high temperature process steps. In addition, the said annihilation of positively charged oxygen vacancies will strongly depend on the layout and design rules. To confirm this, we investigated the effect of active to active spacing on the VT of the HKMG MOS transistors. It is observed that VT increases with increase in active to active spacing for nMOS transistors and decreases for pMOS transistors due to the higher annihilation of the oxygen vacancies at the corners of the active-gate overlap region. It is also found that the dependence of VT on active to active spacing is higher for nMOS transistors with thicker La capping layer thickness, which again confirmed the annihilation of both V0++ and interface dipoles. It is also shown that the observed NWE could be reduced by optimizing the thickness of HfO2, SiO2 interfacial layer, La capping layer and by using the dummy actives. An empirical model for the said NWE is also developed. The accuracy of the model is verified by comparing it with the measurement data. The model can accurately predict the VT of different device geometries and for a wide range of HfO2 and La capping layer thickness. We have discussed the effects of device dimensions on the analog performance of gate-first HKMG MOS transistors. It is observed through detailed measurements that the trans-conductance (gm,) of HKMG MOS transistors increases with reduction in the channel width. The 80nm nMOS and pMOS wide transistors have shown ~28% and ~26% higher intrinsic gain compared to the 1μm wider ones respectively. And 80nm nMOS and pMOS wide transistors have shown ~26% and ~21% improvement in trans-conductance generation efficiency (gm/Id) compared to the 1μm wide transistors respectively. The similar behavior is observed for all gate lengths. This has been attributed to the reduction in the remote coulomb scattering (lower Vo++ in narrower transistors) for narrow width transistors. It is finally shown that longer and narrower HKMG MOS transistors will provide more benefit with respect to the analog performance metrics. We have also studied the analog performance of HKMG MOS transistors for low voltage applications such as mobile applications and medical electronics. It is found that at a lower bias current, the analog performance is marginally better for narrow width HKMG MOS transistors. We have also investigated the effect of active to active spacing on the analog performance of the HKMG MOS transistors and it has been shown that the analog performance is better with increase in active to active spacing due to the higher annihilation of the positively charged oxygen vacancies at the corners of the active-gate overlap region. In addition, we have also shown that the analog performance can further be improved by dividing the single active into multiple actives or by eliminating the active dummies. In this way, the net reduction in V0++ over the total width will be more and the corresponding analog performance will be better.
dc.description.statementofresponsibility by M. Satya Sivanaresh
dc.format.extent xxvii, 143p;col.; ill;
dc.language.iso en_US en_US
dc.publisher Indian Institute of Technology Gandhinagar en_US
dc.title Anomalous narrow width effect in gate first high-K metal gate MOS transistors en_US
dc.type Thesis en_US
dc.contributor.department Electrical Engineering
dc.description.degree Ph.D.


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