Abstract:
The dimensions of the transistor are being aggressively scaled down in order to continuously improve the performance. The semiconductor industry showcase new technology node every two to three years, featuring faster performance and enhanced integration density. The enhancement in integration density has become possible because of scaling of transistor with every technology. The increased number of transistors on chip lead to inclusion of broader functionality on chip. However, all these advantages of technology scaling come at the cost of increased power consumption. The increased sensitivity to process variation at lower technology nosed has worsen this problem. Therefore, it has become very necessary to design low power process variation tolerant circuits. Pulsed latches and semidynamic flip-flops are extensively used in the processor design. Most of the latching mechanism on a microprocessor is done by pulsed latches. Semidynamic flip-flops are extensively used to design high speed pipelines to enhance performance of microprocessor. This work targets to design pulsed latches and semidynamic flip-flops for reduced power consumption in state-of-the-art FinFET technology. The potential of workfunction engineering in FinFET technology to design circuits for reduced power consumption is demonstrated in this work. The proposed workfunction engineered high threshold voltage transistors are selectively used in the standard circuits for power and delay reduction. The delay inverters in semidynamic flip flops and pulse generator of pulsed latches if implemented with these proposed transistors enable significant reduction in power consumption. In order to reduce propagation delay, the contention at internal nodes of brute-force latch and semidynamic flip-flop is reduced using these weak transistors. The proposed circuit designs also show significant improvement in noise immunity and are compact compared to the standard designs.