Guarded dual rail logic for soft error tolerant standard cell library cell library

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dc.contributor.author Kaur, Raminder
dc.date.accessioned 2017-03-23T09:52:52Z
dc.date.available 2017-03-23T09:52:52Z
dc.date.issued 2016
dc.identifier.citation kaur, R. (2016). Guarded dual rail logic for soft error tolerant standard cell library cell library. Indian Institution of Technology, pp. 66. (Acc No: T00150) en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/2772
dc.description.statementofresponsibility by Raminder kaur
dc.format.extent 66 p,: col. ill; 30 cm+.
dc.language.iso en_US en_US
dc.publisher Indian Institute of Technology Gandhinagar en_US
dc.title Guarded dual rail logic for soft error tolerant standard cell library cell library en_US
dc.type Thesis en_US
dc.contributor.department Electrical Engineering
dc.description.degree M.Tech.


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