Compact modeling of gate capacitance in III-V channel quadruple-gate FETs

Show simple item record Yadav, Chandan Ganeriwala, Mohit D. Mohapatra, Nihar Ranjan Agarwal, Amit Chauhan, Yogesh Singh 2017-06-14T08:53:14Z 2017-06-14T08:53:14Z 2017-07
dc.identifier.citation Yadav, Chandan; Ganeriwala, Mohit D.; Mohapatra, Nihar R.; Agarwal, Amit and Chauhan, Yogesh Singh, "Compact modeling of gate capacitance in III-V channel quadruple-gate FETs", IEEE Transactions on Nanotechnology, DOI: 10.1109/TNANO.2017.2709752, July 2017. en_US
dc.identifier.issn 1536-125X
dc.description.abstract In this paper, we present a compact model for charge density and gate capacitance for low effective mass channel material based quadruple-gate FETs (QGFETs). The proposed model accounts for the effect of quantum capacitance and conduction band non-parabolicity, which are important in FETs comprised of the low effective mass channel material. In modeling of QGFET, we propose and use a new form of Fermi-Dirac integral of order -1/2, which matches closely with the numerical data. Our model for the charge density and gate capacitance is compared with 3D TCAD simulations data, and shows excellent match. The proposed explicit compact model can be easily employed in efficient exploration of circuits based on the low effective mass QGFET nanowires. en_US
dc.description.statementofresponsibility by Chandan Yadav, Mohit D. Ganeriwala, Nihar R. Mohapatra, Amit Agarwal and Yogesh Singh Chauhan
dc.format.extent vol.16, no.04, pp.703-710
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject Quantum capacitance en_US
dc.subject Logic gates en_US
dc.subject Numerical models en_US
dc.subject Integrated circuit modeling en_US
dc.subject Field effect transistors en_US
dc.subject Data models en_US
dc.title Compact modeling of gate capacitance in III-V channel quadruple-gate FETs en_US
dc.type Article en_US
dc.relation.journal IEEE Transactions on Nanotechnology

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