Modeling of quantum confinement and capacitance in III-V gate-all-around 1-D transistors

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dc.contributor.author Ganeriwala, Mohit D.
dc.contributor.author Yadav, Chandan
dc.contributor.author Ruiz, Francisco G.
dc.contributor.author Marin, Enrique G.
dc.contributor.author Chauhan, Yogesh Singh
dc.contributor.author Mohapatra, Nihar Ranjan
dc.date.accessioned 2018-01-30T11:28:19Z
dc.date.available 2018-01-30T11:28:19Z
dc.date.issued 2017-12
dc.identifier.citation Ganeriwala, Mohit D.; Yadav, Chandan; Ruiz, Francisco G.; Marin, Enrique G.; Chauhan, Yogesh Singh and Mohapatra, Nihar R., "Modeling of quantum confinement and capacitance in III-V gate-all-around 1-D transistors", IEEE Transactions on Electron Devices, DOI: 10.1109/TED.2017.2766693, vol. 64, no. 12, pp. 4889-4896, Dec. 2017. en_US
dc.identifier.issn 0018-9383
dc.identifier.uri https://doi.org/10.1109/TED.2017.2766693
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/3415
dc.description.abstract In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III-V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering the wave function penetration into the gate insulator, effective mass discontinuity at the semiconductor-oxide interface, 2-D confinement in the NW, and Fermi-Dirac statistics. The semiconductor charge expression proposed in this paper is completely explicit in terms of applied gate voltage, therefore, making it highly suitable for large circuit simulations. The model is also compared with the results from self-consistent Schro?dinger-Poisson solver for different NW sizes and materials and found to be accurate over a wide range of gate voltages.
dc.description.statementofresponsibility by Mohit D. Ganeriwala, Chandan Yadav, Francisco G. Ruiz, Enrique G. Marin, Yogesh Singh Chauhan and Nihar R. Mohapatra
dc.format.extent vol. 64, no. 12, pp. 4889-4896
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject Circuit simulation en_US
dc.subject density of states (DOS) en_US
dc.subject III-V en_US
dc.subject MOS transistor en_US
dc.subject nanowire (NW) en_US
dc.subject quantum capacitance en_US
dc.title Modeling of quantum confinement and capacitance in III-V gate-all-around 1-D transistors en_US
dc.type Article en_US
dc.relation.journal IEEE Transactions on Electron Devices


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