PBTI in HKMG nMOS transistors--effect of width, layout, and other technological parameters

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dc.contributor.author Duhan, Pardeep
dc.contributor.author Rao, V. Ramgopal
dc.contributor.author Mohapatra, Nihar Ranjan
dc.date.accessioned 2018-02-13T08:02:24Z
dc.date.available 2018-02-13T08:02:24Z
dc.date.issued 2017-10
dc.identifier.citation Duhan, Pardeep; Rao, V. Ramgopal and Mohapatra, Nihar Ranjan, “PBTI in HKMG nMOS transistors--effect of width, layout, and other technological parameters”IEEE Transactions on Electron Devices, DOI: 10.1109/TED.2017.2742860, vol. 64, no. 10, pp. 4018-4024, Oct. 2017. en_US
dc.identifier.issn 0018-9383
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/3447
dc.identifier.uri http://dx.doi.org/10.1109/TED.2017.2742860
dc.description.abstract This paper discusses in detail the effects of transistor width, layout, and technological parameters like gate dielectric and Lanthanum capping layer thickness on positive bias temperature instability (PBTI) of nMOS transistors fabricated using 28-nm gate-first High- K metal gate CMOS technology. It is shown that the PBTI reduces with decrease in width ( W ), increase in capping layer thickness and decrease in high- K dielectric thickness. The physical mechanisms responsible for these dependencies are investigated and attributed to the modulation of preexisting traps in the high- K dielectric and the modulation of electron injection into these traps. It is also shown that the PBTI of the devices could be improved by dividing a single active into multiple actives, by increasing active-to-active spacing and gate pitch. en_US
dc.description.statementofresponsibility by Pardeep Duhan, V. Ramgopal Rao and Nihar Ranjan Mohapatra
dc.format.extent Vol. 64, no. 10, pp. 4018-4024,
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject Logic gates en_US
dc.subject Hafnium compounds en_US
dc.subject Electron traps en_US
dc.subject MOSFET en_US
dc.subject Stress en_US
dc.subject Dielectrics en_US
dc.subject Channel width en_US
dc.subject device scaling en_US
dc.subject gate current en_US
dc.subject hafnium dioxide (HfO₂) en_US
dc.title PBTI in HKMG nMOS transistors--effect of width, layout, and other technological parameters en_US
dc.type Article en_US
dc.relation.journal IEEE Transactions on Electron Devices


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