Impact of high-κ spacer on circuit level performance of junctionless FinFET

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dc.contributor.author Surana, Neelam
dc.contributor.author Mekie, Joycee
dc.contributor.author Mohapatra, Nihar Ranjan
dc.contributor.other International Conference on Electron Devices and Solid-State Circuits (EDSSC)
dc.coverage.spatial Hsinchu, TW
dc.date.accessioned 2018-03-15T06:51:50Z
dc.date.available 2018-03-15T06:51:50Z
dc.date.issued 2017-10-18
dc.identifier.citation Surana, Neelam; Mekie, Joycee and Mohapatra, Nihar Ranjan, "Impact of high-? spacer on circuit level performance of junctionless FinFET", in the International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, TW, Oct. 18-20, 2017. en_US
dc.identifier.uri https://doi.org/10.1109/EDSSC.2017.8126574
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/3512
dc.description.abstract This paper shows the circuit level performance comparison of low-? and high-? spacer Junctionless FinFET(J-FinFET). TCAD simulations show that for high-? (HfO2, ?=22) spacer J-FinFET, the device performance parameters such as DIBL (drain induced barrier lowering), SS (sub-threshold swing) and ION/IOFF improved by 14.5 %, 5% and 3.5x respectively as compared to low-? (SiO2, ?=3.9) spacer J-FinFET. Interestingly, the same is not true for the circuit-level parameters. Results of circuit-level performances show that for high-? spacer J-FinFET circuits, delay and power consumption is increased by minimum 40% and 36%, respectively, as compared to their corresponding low-? spacer J-FinFET circuits. Our analysis shows that performance degradation in high-? spacer J-FinFET is due to increased fringe capacitance in high-? spacer J-FinFET.
dc.description.statementofresponsibility by NeelamSurana, Joycee Mekie, and Nihar Ranjan Mohapatra
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.title Impact of high-κ spacer on circuit level performance of junctionless FinFET en_US
dc.type Article en_US


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