Split-gate architecture for higher breakdown voltage in STI based LDMOS transistors

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dc.contributor.author Teja, Subrahmanya
dc.contributor.author Bhoir, Mandar S.
dc.contributor.author Mohapatra, Nihar Ranjan
dc.contributor.other International Conference on Electron Devices and Solid-State Circuits (EDSSC)
dc.coverage.spatial Hsinchu, TW.
dc.date.accessioned 2018-03-27T10:12:55Z
dc.date.available 2018-03-27T10:12:55Z
dc.date.issued 2017-10-18
dc.identifier.citation Teja, Subrahmanya; Bhoir, Mandar and Mohapatra, Nihar R., "Split-gate architecture for higher breakdown voltage in STI based LDMOS transistors", in the International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, TW, Oct. 18-20, 2017. en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/3558
dc.description.statementofresponsibility by Subrahmanya Teja, Mandar Bhoir and Nihar R. Mohapatra,
dc.language.iso en en_US
dc.title Split-gate architecture for higher breakdown voltage in STI based LDMOS transistors en_US
dc.type Article en_US


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