CFCS calibration circuit design for multi-bit pipelined ADC architectures

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dc.contributor.author Gupta, Hari Shanker
dc.contributor.author Mohapatra, Satyajit
dc.contributor.author Pandya, Nisha
dc.contributor.author Mohapatra, Nihar Ranjan
dc.contributor.author Vasoliya, Rohit
dc.contributor.author Mehta, Sanjeev
dc.contributor.author Chowdhury, Arup Roy
dc.date.accessioned 2018-04-18T12:09:51Z
dc.date.available 2018-04-18T12:09:51Z
dc.date.issued 2018-04
dc.identifier.citation Gupta, Hari Shanker; Mohapatra, Satyajit; Pandya, Nisha; Mohapatra, Nihar; Vasoliya, Rohit; Mehta, Sanjeev and Chowdhury, Arup Roy, "CFCS calibration circuit design for multi-bit pipelined ADC architectures", Microsystem Technologies, DOI: 10.1007/s00542-018-3887-1, Apr. 2018. en_US
dc.identifier.isbn 1432-1858
dc.identifier.issn 0946-7076
dc.identifier.uri http://dx.doi.org/10.1007/s00542-018-3887-1
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/3611
dc.description.abstract Design of high resolution ADCs in scaled CMOS technology is challenging due to increased component mismatch, comparator offset, and finite op-amp gain error. In this work, a commutated feedback capacitor switching calibration technique has been proposed to improve the ENOB and linearity of ADCs with multi-bit pipeline architecture. During normal operation of ADC, the fixed sampling capacitor is swapped in the feedback capacitor. We have distributed the sampling capacitor and swap the feedback capacitor with the sampling capacitor(s) in the MDAC of each pipeline stage ADC. The mismatches of different pipeline stages are concurrently corrected in the digital domain. Proposed technique requires digital calibration circuits and requires no extra calibration phase cycles. The prime objective of this work is to achieve high linearity and ENOB in pipeline architectures with low power consumption. Behavioral simulation of 16-bit 5Ms/s pipeline ADC in UMC 0.18 µm double poly triple metal processes with proposed calibration shows significant improvement in DNL with σ = 0.25% capacitor mismatch with correct 16-bit digital output. The design is implemented using HSPICE simulation. The robustness of the proposed technique has been verified by process, temperature and voltage variation simulations and Monte Carlo analysis.
dc.description.statementofresponsibility by Hari Shanker Gupta, Satyajit Mohapatra, Nisha Pandya, Nihar Mohapatra, Rohit Vasoliya, Sanjeev Mehta and Arup Roy Chowdhury
dc.language.iso en en_US
dc.publisher Springer Verlag en_US
dc.title CFCS calibration circuit design for multi-bit pipelined ADC architectures en_US
dc.type Article en_US
dc.relation.journal Microsystem Technologies


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