Single-error hardened and multiple-error tolerant guarded dual modular redundancy technique

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dc.contributor.author Aketi, Sai Aparna
dc.contributor.author Mekie, Joycee
dc.contributor.author Shah, Hemal
dc.contributor.other 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID 2018)
dc.coverage.spatial Pune, IN
dc.date.accessioned 2018-04-27T06:13:14Z
dc.date.available 2018-04-27T06:13:14Z
dc.date.issued 2018-01-06
dc.identifier.citation Aketi, Sai Aparna; Mekie, Joycee and Shah, Hemal, "Single-error hardened and multiple-error tolerant guarded dual modular redundancy technique", in the 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID 2018), Pune, IN, Jan. 6-10, 2018. en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/3634
dc.description.statementofresponsibility by Sai Aparna Aketi, Joycee Mekie and Hemal Shah
dc.language.iso en en_US
dc.title Single-error hardened and multiple-error tolerant guarded dual modular redundancy technique en_US
dc.type Article en_US


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