An ultra energy efficient Neuron enabled by tunneling in sub-threshold regime on a highly manufacturable 32 nm SOI CMOS technology

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dc.contributor.author Chavan, Tanmay
dc.contributor.author Dutta, Sangya
dc.contributor.author Mohapatra, Nihar Ranjan
dc.contributor.author Ganguly, Udayan
dc.contributor.other 76th Device Research Conference (DRC-2018)
dc.coverage.spatial Santa Barbara, US
dc.date.accessioned 2018-09-05T12:48:14Z
dc.date.available 2018-09-05T12:48:14Z
dc.date.issued 2018-07-24
dc.identifier.citation Chavan, T.; Dutta, S.; Mohapatra, Nihar R. and Ganguly, U.,An ultra energy efficient Neuron enabled by tunneling in sub-threshold regime on a highly manufacturable 32 nm SOI CMOS technology, in the 76th Device Research Conference (DRC-2018), University of California, Santa Barbara, US, Jun. 24-27, 2018. en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/3891
dc.description.statementofresponsibility by T. Chavan, S. Dutta, Nihar R. Mohapatra and U. Ganguly
dc.language.iso en en_US
dc.title An ultra energy efficient Neuron enabled by tunneling in sub-threshold regime on a highly manufacturable 32 nm SOI CMOS technology en_US
dc.type Article en_US


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