A computationally efficient compact model for trap-assisted carrier transport through multi-stack gate dielectrics of HKMG nMOS transistors

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dc.contributor.author Ojha, Apoorva
dc.contributor.author Mohapatra, Nihar Ranjan
dc.date.accessioned 2018-10-04T12:52:44Z
dc.date.available 2018-10-04T12:52:44Z
dc.date.issued 2018-09
dc.identifier.citation Ojha, Apoorva and Mohapatra, Nihar R., "A computationally efficient compact model for trap-assisted carrier transport through multi-stack gate dielectrics of HKMG nMOS transistors", IEEE Journal of the Electron Devices Society, DOI: 10.1109/JEDS.2018.2871264, Sep. 2018. en_US
dc.identifier.issn 2168-6734
dc.identifier.uri https://doi.org/10.1109/JEDS.2018.2871264
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/3934
dc.description.abstract This paper analyzes in detail the carrier transport through the multi stack gate dielectric of High-K Metal gate (HKMG) nMOS transistors under different gate biases and temperatures. The existing uncertainty about the carrier transport mechanisms for different gate biases is resolved through accurate band diagram analysis and gate current measurement under different conditions. The Trap Assisted Tunneling (TAT, elastic and inelastic) and Poole-Frenkel (PF) conduction are identified as the two dominant mechanisms of carrier transport. These two mechanisms are found to be prevalent in different gate bias ranges and have distinct signatures. A computationally efficient compact model for the gate current in HKMG nMOS transistors is developed capturing the simultaneity of both the carrier transport mechanisms. The proposed model is valid for all gate voltages (accumulation to inversion) and for different temperatures. The accuracy of the proposed model is confirmed by comparing it with the experimental data.
dc.description.statementofresponsibility by Apoorva Ojha and Nihar R.Mohapatra
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject Logic gates en_US
dc.subject MOSFET en_US
dc.subject Tunneling en_US
dc.subject Computational modeling en_US
dc.subject Electron traps en_US
dc.subject Silicon en_US
dc.subject Temperature measurement en_US
dc.subject Gate tunneling en_US
dc.subject HKMG en_US
dc.subject nelastic en_US
dc.subject Poole Frenkel en_US
dc.subject TAT en_US
dc.subject compact model en_US
dc.subject trap-level en_US
dc.subject phonon-assisted en_US
dc.subject temperature-dependence en_US
dc.subject phonon transition probability en_US
dc.title A computationally efficient compact model for trap-assisted carrier transport through multi-stack gate dielectrics of HKMG nMOS transistors en_US
dc.type Article en_US
dc.relation.journal IEEE Journal of the Electron Devices Society


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