Energy and error analysis framework for approximate computing in mobile applications

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dc.contributor.author Jha, Chandan Kumar
dc.contributor.author Ved, Sneha N.
dc.contributor.author Anand, Ishant
dc.contributor.author Mekie, Joycee
dc.date.accessioned 2019-05-16T09:04:37Z
dc.date.available 2019-05-16T09:04:37Z
dc.date.issued 2019-05
dc.identifier.citation Jha, Chandan Kumar; Ved, Sneha N.; Anand, Ishant and Mekie, Joycee, “Energy and error analysis framework for approximate computing in mobile applications”, IEEE Transactions on Circuits and Systems II: Express Briefs, DOI: 10.1109/TCSII.2019.2910137, May 2019. en_US
dc.identifier.issn 1549-7747
dc.identifier.uri https://doi.org/10.1109/TCSII.2019.2910137
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/4416
dc.description.abstract In this brief we propose a framework that enables us to analyse energy and error for mobile applications when run on systems with approximate circuits. Approximate circuits have conventionally been used in image/video processing applications, which are mostly limited to 8-bits. To the best of our knowledge this is the first work where approximate circuits have been evaluated on a 32-bit processor running real mobile applications. We observe that in approximate adders where Carry is approximated, with 2-bit approximation in LSB, the absolute average error in image processing applications is 3. However, in mobile applications approximation in Carry can lead to an overflow. Hence, approximate adders with Carry approximation are not suitable for mobile computing. We also show the role of data dependent switching in energy consumption and highlight which input pattern should not be approximated to obtain lesser error. In this brief, we also propose design of three energy-efficient approximate hybrid CMOS full-adders with varying levels of inaccuracies. The adder designs are implemented in UMC 65nm technology using Cadence Virtuoso. Compared to existing approximate adders, on an average, the proposed adders consume 44% lesser energy and have 2× lesser energy delay product. Our proposed adder designs have similar leakage power as compared to the existing adders. en_US
dc.description.statementofresponsibility by Chandan Kumar Jha, Sneha N Ved, Ishant Anand and Joycee Mekie
dc.language.iso en_US en_US
dc.publisher Institute of Electrical and Electronics Engineers en_US
dc.subject Approximate computing en_US
dc.subject Energy and error analysis en_US
dc.subject Gem5 simulator en_US
dc.subject Approximate adder en_US
dc.subject Hybrid CMOS logic en_US
dc.title Energy and error analysis framework for approximate computing in mobile applications en_US
dc.type Article en_US
dc.relation.journal IEEE Transactions on Circuits and Systems II: Express Briefs


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