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Effects of Small Geometries on the Performance of Gate First High- \kappa Metal Gate NMOS Transistors

Walke, A.M.; Mohapatra, Nihar Ranjan (Institute of Electrical and Electronics Engineers (IEEE), 2012-08)

This paper discusses in detail the effect of small geometries on the performance of NMOS transistors fabricated using a 28-nm gate-first CMOS technology. It is shown that the threshold voltage and transconductance of the ...
A zero-cost technique to improve ON-state performance and reliability of power LDMOS transistors

Kaushal, Neeraj Kumari; Mohapatra, Nihar Ranjan (Institute of Electrical and Electronics Engineers, 2021-02)

In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask ...

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