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  • Ganeriwala, Mohit D.; Ruiz, Francisco G.; Marin, Enrique G.; Mohapatra, Nihar Ranjan (IEEE, 2018-09)
    Considering the demand of III-V multigate (MUG) transistors for next-generation CMOS technologies, a compact model is required to test their performance in different circuits. The low effective mass and highly confined ...
  • Ganeriwala, Mohit D.; Yadav, Chandan; Ruiz, Francisco G.; Marin, Enrique G.; Chauhan, Yogesh Singh; Mohapatra, Nihar Ranjan (IEEE, 2017-12)
    In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III-V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor ...

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