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Compact modeling of gate capacitance in III-V channel quadruple-gate FETs

Yadav, Chandan; Ganeriwala, Mohit D.; Mohapatra, Nihar Ranjan; Agarwal, Amit; Chauhan, Yogesh Singh (IEEE, 2017-07)
Modeling of quantum confinement and capacitance in III-V gate-all-around 1-D transistors

Ganeriwala, Mohit D.; Yadav, Chandan; Ruiz, Francisco G.; Marin, Enrique G.; Chauhan, Yogesh Singh; Mohapatra, Nihar Ranjan (IEEE, 2017-12)

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Author
- Chauhan, Yogesh Singh (2)
- Ganeriwala, Mohit D. (2)
- Mohapatra, Nihar Ranjan (2)
- Yadav, Chandan (2)
- Agarwal, Amit (1)
- Marin, Enrique G. (1)
- Ruiz, Francisco G. (1)
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- 2017 (2)