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Now showing items 1-6 of 6

A channel stress-profile based compact model for thereshold voltage prediction of uniaxial strained HKMG nMOS transistors

Ojha, Apoorva; Chauhan, Yogesh Singh; Mohapatra, Nihar Ranjan (IEEE Xplore Digital Library, 2016-03)
Compact modeling of gate capacitance in III-V channel quadruple-gate FETs

Yadav, Chandan; Ganeriwala, Mohit D.; Mohapatra, Nihar Ranjan; Agarwal, Amit; Chauhan, Yogesh Singh (IEEE, 2017-07)
Modeling of quantum confinement and capacitance in III-V gate-all-around 1-D transistors

Ganeriwala, Mohit D.; Yadav, Chandan; Ruiz, Francisco G.; Marin, Enrique G.; Chauhan, Yogesh Singh; Mohapatra, Nihar Ranjan (IEEE, 2017-12)
Predictive effective mobility model for FDSOI transistors using technology parameters

Kushwaha, Pragya; Agarwal, Harshit Kumar; Chauhan, Yogesh Singh; Bhoir, Mandar S.; Mohapatra, Nihar Ranjan; Khandelwal, Sourabh; Duarte, Juan P.; Lin, Yen-Kai; Chang, Huan-Lin; Hu, Chenming (2016-08-03)
Impact of substrate on the frequency behavior of trans-conductance in ultrathin body and BOX FDSOI MOS devices - a physical insight

Bhoir, Mandar S.; Kushwaha, Pragya; Chauhan, Yogesh Singh; Mohapatra, Nihar Ranjan (2017-04-24)
Back-gate bias and substrate doping influenced substrate effect in UTBB FD-SOI MOS transistors: analysis and optimization guidelines

Bhoir, Mandar S.; Chauhan, Yogesh Singh; Mohapatra, Nihar Ranjan (IEEE, 2019-02)

Now showing items 1-6 of 6