Search

Filters

Use filters to refine the search results.

Now showing items 1-7 of 7

Analog performance of gate-first HKMG NMOS transistors - Role of device dimensions and layout

Mohapatra, Nihar Ranjan; Naresh, Satya Siva; Duhan, Pardeep (IEEE, 2015-04)
Width and layout dependence of HC and PBTI induced degradation in HKMG nMOS transistors

Duhan, Pardeep; Ramgopal Rao, V.; Mohapatra, Nihar Ranjan (IEEE, 2016-04-17)
Compact modeling of gate capacitance in III-V channel quadruple-gate FETs

Yadav, Chandan; Ganeriwala, Mohit D.; Mohapatra, Nihar Ranjan; Agarwal, Amit; Chauhan, Yogesh Singh (IEEE, 2017-07)
PBTI in HKMG nMOS transistors--effect of width, layout, and other technological parameters

Duhan, Pardeep; Rao, V. Ramgopal; Mohapatra, Nihar Ranjan (IEEE, 2017-10)
A computationally efficient compact model for trap-assisted carrier transport through multi-stack gate dielectrics of HKMG nMOS transistors

Ojha, Apoorva; Mohapatra, Nihar Ranjan (IEEE, 2018-09)
Source underlap-a novel technique to improve safe operating area and output-conductance in LDMOS transistors

Bhoir, Mandar S.; Kaushal, Kumari Neeraj; Panda, Soumya R.; Singh, Amit K.; Jatana, H. S.; Mohapatra, Nihar R. (Institute of Electrical and Electronics Engineers, 2019-11)
Band-to-band tunneling based ultra-energy-efficient silicon neuron

Chavan, Tanmay; Dutta, Sangya; Mohapatra, Nihar Ranjan; Ganguly, Udayan (Institute of Electrical and Electronics Engineers, 2020-06)

Now showing items 1-7 of 7