Author

Author

Sort by: Order: Results:

  • Duhan, Pardeep; Ganeriwala, Mohit D.; Rao, V. Ramgopal; Mohapatra, Nihar Ranjan (IEEE, 2015-08)
    This letter analyzes the width dependence of gate current observed in nMOS transistors fabricated using the 28-nm gate-first CMOS process. It is experimentally shown that the gate current density is ~10× lower for 80-nm ...
  • Ganeriwala, Mohit D.; Ruiz, Francisco G.; Marin, Enrique G.; Mohapatra, Nihar Ranjan (IEEE, 2018-09)
    Considering the demand of III-V multigate (MUG) transistors for next-generation CMOS technologies, a compact model is required to test their performance in different circuits. The low effective mass and highly confined ...
  • Ganeriwala, Mohit D.; Ruiz, Francisco G.; Marin, Enrique G.; Mohapatra, Nihar Ranjan (Springer Nature, 2019-08)
    The III–V materials have a highly non-parabolic band structure that significantly affects the MOS transistor electrostatics. The compact models used to simulate circuits involving III–V MOS transistors must account for ...
  • Yadav, Chandan; Ganeriwala, Mohit D.; Mohapatra, Nihar Ranjan; Agarwal, Amit; Chauhan, Yogesh Singh (IEEE, 2017-07)
    In this paper, we present a compact model for charge density and gate capacitance for low effective mass channel material based quadruple-gate FETs (QGFETs). The proposed model accounts for the effect of quantum capacitance ...
  • Mohapatra, Nihar Ranjan; Ganeriwala, Mohit D.; Sivanaresh M., Satya (Institute of Electrical and Electronics Engineers, 2016-07)
    This paper experimentally shows the reduction of anomalous narrow width effect (NWE) observed in gate-first high- k metal-gate (HKMG) nMOS transistors by using pregate carbon implants. The experiments are performed with ...
  • Ganeriwala, Mohit D.; Yadav, Chandan; Mohapatra, Nihar Ranjan; Khandelwal, Sourabh (Institute of Electrical and Electronics Engineers (IEEE), 2016-11)
    In this paper we present a compact model for semiconductor charge and quantum capacitance in III-V channel FETs. With III-V being viewed as the most promising candidate for future technology node, a compact model is needed ...
  • Ganeriwala, Mohit D.; Yadav, Chandan; Ruiz, Francisco G.; Marin, Enrique G.; Chauhan, Yogesh Singh; Mohapatra, Nihar Ranjan (IEEE, 2017-12)
    In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III-V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor ...

Search Digital Repository


Browse

My Account