Singh, Sarabjeet; Surana, Neelam; Jain, Pranjali; Mekie, Joycee; Awasthi, Manu
(Cornell University Library, 2021-10)
In this paper, we propose a 'full-stack' solution to designing high capacity and low latency on-chip cache hierarchies by starting at the circuit level of the hardware design stack. First, we propose a novel Gain Cell (GC) ...