Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder

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dc.contributor.author Bharti, Pramod Kumar
dc.contributor.author Surana, Neelam
dc.contributor.author Mekie, Joycee
dc.date.accessioned 2019-11-19T11:29:02Z
dc.date.available 2019-11-19T11:29:02Z
dc.date.issued 2019-11
dc.identifier.citation Bharti, Pramod Kumar; Surana, Neelam and Mekie, Joycee, "Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder", IET Computers & Digital Techniques, DOI: 10.1049/iet-cdt.2019.0019, vol. 13, no. 6, pp. 505-513, Nov. 2019. en_US
dc.identifier.issn 1751-8601
dc.identifier.issn 1751-861X
dc.identifier.uri https://doi.org/10.1049/iet-cdt.2019.0019
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/4960
dc.description.abstract Wide-spread availability of high-speed INTERNET and rapid increase of smart-phone users have significantly increased online video surfing. Video decoders like H.264/H.265/MPEG consume a significant amount of power in Static Random Access Memory (SRAM) buffers. In this study, the authors propose a 1?kb (32?�?32) heterogeneous 8T SRAM architectures with (2-lower order bits) and without truncation for H.264 video decoder. They have used heterogeneous sized SRAM design and bit-truncation techniques are used simultaneously to obtain low power memory design for the H.264 video decoder. They show that the proposed approximate memory used for H.264 video decoder provide high video quality even at low power and low area budget of 0.3?�W/pixel and 5.2?�m 2 /pixel, respectively, at 0.5?V and 20?MHz in UMC 28?nm CMOS technology. The proposed memory architecture is compared with existing approximate memories such as heterogeneous 6T, hybrid 8T/6T, all-identical 6T, and all-identical 8T SRAM memory. The results show that proposed memory architectures perform cumulatively better than existing techniques in terms of dynamic power, leakage power, and area.
dc.description.statementofresponsibility by Pramod Kumar Bharti, Neelam Surana and Joycee Mekie
dc.format.extent vol. 13, no. 6, pp. 505-513
dc.language.iso en_US en_US
dc.publisher Institution of Engineering and Technology en_US
dc.subject video coding en_US
dc.subject CMOS integrated circuits en_US
dc.subject memory architecture en_US
dc.subject SRAM chips en_US
dc.subject low-power electronics en_US
dc.subject decoding en_US
dc.subject integrated circuit design en_US
dc.title Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder en_US
dc.type Article en_US
dc.relation.journal IET Computers & Digital Techniques


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