Source underlap-a novel technique to improve safe operating area and output-conductance in LDMOS transistors

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dc.contributor.author Bhoir, Mandar S.
dc.contributor.author Kaushal, Kumari Neeraj
dc.contributor.author Panda, Soumya R.
dc.contributor.author Singh, Amit K.
dc.contributor.author Jatana, H. S.
dc.contributor.author Mohapatra, Nihar R.
dc.date.accessioned 2019-11-19T11:29:02Z
dc.date.available 2019-11-19T11:29:02Z
dc.date.issued 2019-11
dc.identifier.citation Bhoir, Mandar S.; Kaushal, Kumari Neeraj; Panda, Soumya R.; Singh, Amit K.; Jatana, H. S. and Mohapatra, Nihar R., "Source underlap-a novel technique to improve safe operating area and output-conductance in LDMOS transistors", IEEE Transactions on Electron Devices, DOI: 10.1109/TED.2019.2942372, vol. 66, no. 11, pp. 4823-4828, Nov. 2019. en_US
dc.identifier.issn 0018-9383
dc.identifier.uri https://doi.org/10.1109/TED.2019.2942372
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/4961
dc.description.abstract In this article, we have proposed a simple, novel, and cost-effective technique to mitigate the ON-state performance issues in laterally diffused MOS (LDMOS) transistors. We propose a novel technique-LDMOS transistor with source-side underlap (SU), which can be integrated into any existing LDMOS/bipolar-CMOS-DMOS (BCD) process flow without any additional processing/area cost. Unlike commonly used solutions, the SU LDMOS provides flexibility to improve ON-state behavior without disturbing other performance metrics. The proposed SU LDMOS transistor is experimentally demonstrated using 180-nm CMOS technology, and noteworthy improvement in ON-state breakdown voltage, electrical safe operating area (SOA), output conductance, transistor intrinsic gain, and cutoff frequency is reported. The physics behind the improvement is also discussed in detail.
dc.description.statementofresponsibility by Mandar S. Bhoir, Kumari Neeraj Kaushal, Soumya R. Panda, Amit K. Singh, H. S. Jatana and Nihar R.
dc.format.extent vol. 66, no. 11, pp. 4823-4828
dc.language.iso en_US en_US
dc.publisher Institute of Electrical and Electronics Engineers en_US
dc.subject Transistors en_US
dc.subject Doping en_US
dc.subject Logic gates en_US
dc.subject Standards en_US
dc.subject Implant en_US
dc.subject Physics en_US
dc.subject Electric breakdown en_US
dc.title Source underlap-a novel technique to improve safe operating area and output-conductance in LDMOS transistors en_US
dc.type Article en_US
dc.relation.journal IEEE Transactions on Electron Devices


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