Fixed-posit: a floating-point representation for error-resilient applications

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dc.contributor.author Gohil, Varun
dc.contributor.author Walia, Sumit
dc.contributor.author Mekie, Joycee
dc.contributor.author Awasthi, Manu
dc.coverage.spatial United States of America
dc.date.accessioned 2021-05-14T05:18:42Z
dc.date.available 2021-05-14T05:18:42Z
dc.date.issued 2021-10
dc.identifier.citation Gohil, Varun; Walia, Sumit; Mekie, Joycee and Awasthi, Manu, “Fixed-posit: a floating-point representation for error-resilient applications”, IEEE Transactions on Circuits and Systems II: Express Briefs, DOI: 10.1109/TCSII.2021.3072217, vol. 68, no. 10, pp. 3341-3345, Oct. 2021. en_US
dc.identifier.issn 1549-7747
dc.identifier.issn 1558-3791
dc.identifier.uri https://doi.org/10.1109/TCSII.2021.3072217
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/6427
dc.description.abstract Today, almost all computer systems use IEEE-754 floating point to represent real numbers. Recently, posit was proposed as an alternative to IEEE-754 floating point as it has better accuracy and a larger dynamic range. The configurable nature of posit, with varying number of regime and exponent bits, has acted as a deterrent to its adoption. To overcome this shortcoming, we propose fixed-posit representation where the number of regime and exponent bits are fixed, and present the design of a fixed-posit multiplier. We evaluate the fixed-posit multiplier on error-resilient applications of AxBench and OpenBLAS benchmarks as well as neural networks. The proposed fixed-posit multiplier has 47%, 38.5%, 22% savings for power, area and delay respectively when compared to posit multipliers and up to 70%, 66%, 26% savings in power, area and delay respectively when compared to 32-bit IEEE-754 multiplier. These savings are accompanied with minimal output quality loss (1.2% average relative error) across OpenBLAS and AxBench workloads. Further, for neural networks like ResNet-18 on ImageNet we observe a negligible accuracy loss (0.12%) on using the fixed-posit multiplier.
dc.description.statementofresponsibility by Varun Gohil, Sumit Walia, Joycee Mekie and Manu Awasthi
dc.format.extent vol. 68, no. 10, pp. 3341-3345
dc.language.iso en_US en_US
dc.publisher Institute of Electrical and Electronics Engineers en_US
dc.subject IEEE-754 floating point en_US
dc.subject Posit en_US
dc.subject Multipliers en_US
dc.subject Intel Pin en_US
dc.subject Power and Error analysis. en_US
dc.title Fixed-posit: a floating-point representation for error-resilient applications en_US
dc.type Article en_US
dc.relation.journal IEEE Transactions on Circuits and Systems II: Express Briefs


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