Circuit-aware device modeling of energy-efficient monolayer WS2 trench-FinFETs

Show simple item record Agarwal, Tarun Lee, Youseung Luisier, Mathieu 2021-05-14T05:18:45Z 2021-05-14T05:18:45Z 2021-04
dc.identifier.citation Agarwal, Tarun; Lee, Youseung and Luisier, Mathieu, “Circuit-aware device modeling of energy-efficient monolayer WS2 trench-FinFETs”, arXiv, Cornell University Library, DOI: arXiv:2104.07891, Apr. 2021. en_US
dc.description.abstract The continuous scaling of semiconductor technology has pushed the footprint of logic devices below 50 nm. Currently, logic standard cells with one single fin are being investigated to increase the integration density, although such options could severely limit the performance of individual devices. In this letter, we present a novel Trench (T-) FinFET device, composed of a monolayer two-dimensional (2D) channel material. The device characteristics of a monolayer WS2-based T-FinFET are studied by combining the first-principles calculations and quantum transport (QT) simulations. These results serve as inputs to a predictive analytical model. The latter allows to benchmark the T-FinFET with strained (s)-Si FinFETs in both quasi-ballistic and diffusive transport regimes. The circuit-level evaluation highlights that WS2 T-FinFETs exhibit a competitive energy-delay performance compared to s-Si FinFET and WS2 double-gate transistors, assuming the same mobility and contact resistivity at small footprints.
dc.description.statementofresponsibility by Tarun Agarwal, Youseung Lee and Mathieu Luisier
dc.language.iso en_US en_US
dc.publisher Cornell University Library en_US
dc.subject 2D materials en_US
dc.subject monolayer WS2 FinFET en_US
dc.subject multi-scale modeling en_US
dc.subject benchmarking en_US
dc.subject strained-Si FinFETs. en_US
dc.title Circuit-aware device modeling of energy-efficient monolayer WS2 trench-FinFETs en_US
dc.type Pre-Print en_US
dc.relation.journal arXiv

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